1. Field of the Invention
The present invention relates to a semiconductor device, and particularly a semiconductor device which can suppress occurrence of crystal defects in a semiconductor substrate during and after manufacturing of the semiconductor device.
2. Description of the Background Art
In recent years, a flash memory which is a kind of nonvolatile semiconductor memory device has been expected as a useful memory device for the next generation because it can be manufactured at a lower cost than a Dynamic Random Access Memory (DRAM). A memory cell of a flash memory includes a source region connected to a corresponding source line, a drain region connected to a corresponding bit line, a floating gate electrode for storing information and a control gate electrode connected to a corresponding word line.
An FN (Fowler Nordheim) current phenomenon, a channel hot electron phenomenon or the like is caused in a gate insulating film formed of a tunnel oxide film, which is located immediately under the floating gate electrode, for injecting electrons into the floating gate electrode or removing electrons accumulated in the floating gate electrode so that erasing or writing of information is performed. As a result of the foregoing injection and removal of electrons with respect to the floating gate electrode, a binary state of the threshold is determined according to the state of electrons in the floating gate electrode, and xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is read out depending on this binary state.
A memory cell array structure of an NOR (Not OR) type is used most generally in a nonvolatile semiconductor memory of a floating gate type such as a flash memory of the foregoing structure and other EEPROMs (Electrically Erasable and Programmable Read Only Memories) including floating gate electrodes.
The NOR type array is provided with contacts, which are connected to drain regions of memory cells in respective rows. Bit lines are formed in the row direction. Each bit line is formed of, e.g., an interconnection of a policide structure of metal silicide and polycrystalline silicon or a metal interconnection. Gate interconnections of memory cells in respective columns are formed in the column direction. The bit lines and columns lines are arranged in a matrix form.
An example of a planar structure of conventional flash memories is shown in FIG. 43. As shown in FIG. 43, control gate electrodes 112a, 112b, 112c and 112d which are spaced from each other extend across a plurality of element formation regions S, which are isolated from each other by trench isolating oxide films 103. Floating gate electrodes 110a, 110b, 110c and 110d, which are located immediately under control gate electrodes 112a, 112b, 112c and 112d, are formed in portions where these control gate electrodes cross element formation regions S, respectively.
A source regions 106a is formed, e.g., in one of element formation regions S located on the opposite sides of control gate electrode 112b, and a drain region 104b is formed in the other element formation region S. Each drain region is electrically connected to the bit line (not shown) via a contact hole 117.
The source regions are electrically connected together by an impurity region of a predetermined conductivity type, which is formed in a silicon substrate portion located immediately under a region between control gate electrodes 112a and 112b. The above source region structure in the memory cells is particularly referred to as a self-align source structure. In the self-align source structure, the source regions of the respective memory cells are not connected by an interconnection via a contact, but are connected by a diffusion layer interconnection. In other words, the diffusion layer interconnection includes the source regions.
A method of manufacturing a self-align source structure will now be described. A photoresist pattern (not shown) is formed over an entire area except for the region defined between control gate electrodes 112a and 112b shown in FIG. 43 and others, where the source regions are to be formed, respectively.
Using the photoresist pattern and control gate electrodes 112a and 112b as a mask, etching is effected to remove trench isolating oxide films 103 located in the region between control gate electrodes 112a and 112b so that the surfaces of silicon substrate located immediately under trench isolating oxide films 103 are exposed.
Then, ions of a predetermined conductivity type are implanted into the exposed surfaces of silicon substrate located between control gate electrodes 112a and 112b so that the respective source regions are formed, and the diffusion layer interconnection connecting the respective source regions in the column direction is formed in a self-aligned fashion.
Thereby, a sectional structure shown in FIG. 44 is formed. In FIG. 44, which is a cross section taken along section line XLIVxe2x80x94XLIV in FIG. 43, a diffusion layer interconnection 106 including the source regions is formed in a self-aligned fashion at the surface of silicon substrate 102, which includes the surfaces of grooves 102a, and is exposed by removal of trench isolating oxide films 103. This diffusion layer interconnection 106 forms the source region in a portion (i.e., a region between grooves 102a) of the main surface of silicon substrate 102.
In a sectional structure shown in FIG. 45, which is a cross section taken along line XLVxe2x80x94XLV in FIG. 45, trench isolating oxide films 103 are removed from the region between control gate electrodes 112a and 112b as well as the region between control gate electrodes 112c and 112d so that openings 103 exposing the surface of silicon substrate 102 (bottoms of grooves 102a) are formed. Diffusion layer interconnections 106 including source regions are formed at the exposed surface portions of silicon substrate 102.
Thereafter, sidewall insulating films 114a are formed on side surfaces of control gate electrodes 112a-112d including the side surfaces of openings 103a, as shown in FIGS. 44 and 45. Then, a TEOS (Tetra Ethyl Ortho Silicate glass) film 115 covering control gate electrodes 112a-112d is formed.
Then, as shown in FIGS. 46 and 47, a BPTEOS (Boro Phospho Tetra Ethyl Ortho Silicate glass) film 116 which will form an interlayer insulating film is then formed on TEOS film 115. Then, as shown in FIGS. 48 and 49, thermal processing or polishing is effected to smoothen the surface of BPTEOS film 116. In these manners, a major portion of the flash memory of the NOR type array is completed.
According to this flash memory, the self-align source structure is employed in the source region of memory cell so that it is not necessary to make an electrical connection between the source regions via contacts. Thus, the source region of memory cell is formed in the region defined between the neighboring two control gate electrodes according to design rules, and therefore the memory cells can be miniaturized and/or can be arranged at high density.
According to the flash memory employing the self-align source structure, as described above, the source region is formed in the region defined between the neighboring two control gate electrodes according to the minimum design rule so that the memory cells can be miniaturized.
Further, the trench isolating structure which uses trench isolating oxide film 103 is used as the isolating structure for electrically isolating the elements, as described above. This trench isolation structure allows further miniaturization compared with a conventional LOCOS isolation structure. In the trench isolation structure, groove 102a having relatively steep side surfaces is formed in silicon substrate 102, and is filled with the oxide film to form trench isolating oxide film 103, as shown in FIG. 44.
However, when forming the source region of the self-aligned structure in the flash memory described above, trench isolating oxide film 103 filling groove 102a is removed from a portion or region between the neighboring two control gate electrodes so that opening 103a exposing the surface of silicon substrate (groove 102a) is formed.
As shown in FIG. 50 or 51, opening 103a has a substantial depth which is equal to a value obtained by adding a thickness(es) of control gate electrode 112a-112d and floating gate electrode 110a-110d to a depth of groove 102a, and opening 103a forms the deepest opening in the pattern formed on silicon substrate 2.
FIG. 51 is a cross section showing a sectional structure of a portion near the element formation region and taken along line LIxe2x80x94LI in FIG. 43. In FIG. 51, floating gate electrodes 110a-110d are formed under control gate electrodes 112a-112d with an ONO film 109 therebetween, respectively.
Since opening 103a is the deepest portion, a large stress acts on silicon substrate 102 located on the bottom of opening 103a surrounded by dotted line B after BPTEOS film 116 serving as the interlayer insulating film is formed within opening 103a. This stress may cause crystal defects in silicon substrate 102 during a later manufacturing step. Also, the stress may cause crystal defects in silicon substrate 102 of the completed semiconductor device.
In the memory cell region of the flash memory having the self-aligned structure, opening 103a formed in the region between the two neighboring control gate electrodes is filled with the interlayer insulating film such as BPTEOS film 116 as described above. This increases the stress particularly in a portion of silicon substrate 102 located on the bottom of opening 103a, and thereby increases the possibility of occurrence of crystal defects in silicon substrate 102.
The crystal defects in silicon substrate 102 may cause, e.g., a leak current, and thereby may impede intended operations of the flash memory. Further, the crystal defects may impede intended operations as the semiconductor device, resulting in reduction in yield of the semiconductor devices.
When the flash memories are miniaturized to a further extent from now on, the aspect ratio of this opening will further increase, and it can be estimated that the stress acting on the above portion of the silicon substrate will further increase. As a result, crystal defects will be more liable to occur in the silicon substrate, resulting in further reduction in reliability of the operation of the semiconductor device as well as reduction in yield.
The invention is intended to overcome the possible problems described above, and an object of the invention is to provide a semiconductor device, which can suppress occurrence of crystal defects in a semiconductor substrate, and thereby can ensure high reliability of operations and high yield.
According to a first aspect of the invention, a semiconductor device includes a semiconductor substrate having a main surface, a groove, a first insulating film, two conductive layers, an opening, a second insulating film and a void. The groove is formed at the main surface of the semiconductor substrate. The first insulating film fills the groove. The two conductive layers are formed on the first insulating film with a space between each other. The opening is formed in the first insulating film, and exposes the surface of the semiconductor substrate located immediately under the first insulating film located between two interconnections. The second insulating film fills the opening, and covers the two conductive layers. The void is formed in the opening filled with the second insulating film.
According to this structure, the void formed in the opening reduces a stress, which acts on the semiconductor substrate particularly in a bottom portion of the opening, in manufacturing steps of the semiconductor device after formation of the second insulating film. In addition to the stages during manufacturing, the void also reduces the stress acting on the semiconductor substrate of the completed semiconductor device. The reduction in stress suppresses occurrence of crystal defects in the semiconductor substrate, and therefore can prevent disadvantages such as a leak current so that intended operations of the semiconductor device are ensured, and the yield is improved.
Preferably, the void extends from a position between the first insulating films to a position between the two conductive layers.
In this case, the void located between the two conductive layers reduces a capacitance between the two conductive layers so that the operation speed of the semiconductor device can be increased.
More preferably, the semiconductor device includes an element formation region crossing the two conductive layers, and isolated by the first insulating film, an impurity region on one side of a predetermined conductivity type formed in the element formation region on the side remote from one of the two conductive layers and near the other conductive layer, and another impurity region on a different side of a predetermined conductivity type formed in the element formation region on the side remote from the other conductive layer. The conductive layer includes a first electrode portion formed on the element formation region, and a second electrode portion formed on the first electrode portion.
According to the above aspect, a semiconductor element including the first and second electrode portions as well as the impurity regions on the one and the other sides is obtained at the element formation region.
More preferably, the semiconductor device includes a conductive region formed at the surface of the semiconductor substrate located in the region between the two conductive layers, and the conductive region includes the impurity region on the one side.
In the above structure, the impurity region on the one side of the semiconductor element is electrically connected to another portion by the conductive region.
More preferably, the first electrode portion includes a floating gate, the second electrode portion includes a control gate, the impurity region on the one side includes a source region, and the impurity region on the other side includes a drain region.
In this structure, a memory cell including the floating gate, control gate, source region and drain region is formed as a semiconductor element.
According to a second aspect of the invention, a semiconductor device includes a semiconductor substrate, a groove, an element isolation insulating film, an element formation region, a first gate interconnection, a second gate interconnection, a source region, a drain region, a conductive region, an opening, an interlayer insulating film and a void. The groove is formed at the semiconductor substrate. The element isolating and insulating film fills the groove. The element formation region is formed at the semiconductor substrate, and is isolated by the element isolating and insulating film. The first gate interconnection is formed across the element isolating and insulating film and the element formation region, and includes a floating gate electrode and a control gate electrode. The second gate interconnection is formed across the element isolating and insulating film and the element formation region, is spaced from the first gate interconnection, and includes the floating gate electrode and the control gate electrode. The source region is formed in the element formation region located between the first and second gate interconnections. The drain region is formed in the element formation region spaced from the source region with the first gate interconnection therebetween. The conductive region includes the source region, and is formed in a region of the semiconductor substrate located between the first and second gate interconnections. The opening is formed in the element isolating and insulating film located between the first and second gate interconnections, and exposes the surface of the semiconductor substrate forming the groove. The interlayer insulating film fills the opening, covers the first and second gate interconnections and is formed on the semiconductor substrate. The void is formed in the opening filled with the element isolating and insulating film.
According to this structure, the memory cell including the floating gate, control gate, source region and drain region can be configured such that the void formed in the opening reduces a stress acting on the semiconductor substrate, which is located on the bottom of the opening, during the manufacturing after formation of the interlayer insulating film. In the completed semiconductor device, the above void reduces the stress acting on the semiconductor substrate. Thereby, occurrence of crystal defects in the semiconductor substrate is suppressed, and disadvantages such as a leak current can be prevented so that intended operations of the memory cell can be ensured, and the yield of the semiconductor device can be improved.
Preferably, the void extends from a position between the element isolating and insulating films to a position between the first and second gate interconnections.
In this structure, the void located between the first and second gate interconnections reduces the line-to-line capacitance between the first and second gate interconnections so that the semiconductor device can operate fast.
According to a third aspect of the invention, a semiconductor device includes a semiconductor substrate, a first insulating film, two interconnections, an opening, a second insulating film and a void. The first insulating film is formed on the semiconductor substrate. The two interconnections are formed on the first insulating film with a space between each other. The opening is formed at the first insulating film located between the two interconnections, and exposes the surface of the semiconductor substrate. The second insulating film fills the opening, covers the interconnections and is formed on the semiconductor substrate. The void is formed in the opening filled with the second insulating film.
According to this structure, the void formed in the opening reduces a stress acting particularly on the semiconductor substrate, which is located on the bottom of the opening, during the manufacturing after formation of the second insulating film. In the completed semiconductor device, the above void reduces the stress acting on the semiconductor substrate. Thereby, occurrence of crystal defects in the semiconductor substrate is suppressed, and disadvantages such as a leak current can be prevented so that intended operations can be ensured, and the yield of the semiconductor device can be high.
Preferably, the void extends from a position between the first insulating films to a position between the two interconnections.
In this structure, the void located between the two interconnections reduces the line-to-line capacitance between the two interconnections so that the semiconductor device can operate fast.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.